The present invention relates to a processor, an encoder, a decoder, and an electronic apparatus. Typically, the present invention can be applied to an encoder and a decoder, which are provided for processing an audio signal. By virtue of the present invention, hardware can be configured to allow instructions each specifying a bit count to be executed to carry out unpacking and packing processes so that variable-length coded data can be processed at a high speed and a low power consumption while maintaining the general-purpose characteristic of the hardware at a high level.
Traditionally, in a processor serving as a processing circuit for executing a variety of programs, various kinds of processing can be carried out at a high speed by adoption of the so-called pipeline-processing technique. FIG. 22 is a block diagram showing a pipeline process carried out by an ordinary processor 1. In the configuration shown in the figure, the processor 1 has a five-stage pipeline. The five stages of the pipeline are an IF stage, a REG stage, an EXE stage, a MEM stage, and a WB stage. At the IF stage, an instruction is fetched from a memory 2. At the REG stage, the instruction is decoded and data is fetched from a core register. At the EXE stage, the instruction is executed by an ALU (Arithmetic Logic Unit) in accordance with a result of the decoding process carried out at the REG stage. At the MEM stage, data is input from and/or output to the memory 2 by way of a bus. At the WB stage, data is written back into the core register. By carrying out the processes at the stages described above, instructions and pieces of data are transferred sequentially from a component to another in the processor 1 and processed by the arithmetic logic unit.
In a variable-length coding process, video and audio signals are compressed. In this case, data to be compressed is a data series having a fixed bit count. The data series is compressed to produce pieces of data having different bit counts. The variable-length pieces of data are concatenated with each other to generate a continuous bit stream.
In a processor for encoding and decoding data of such a kind, a barrel-shift processing unit is used for carrying out an unpacking process. In the unpacking process, the bit stream is decoded to sequentially generate pieces of encoded data having different bit counts. A packing process using the barrel-shift processing unit is an inverse process of the unpacking process. In the packing process, pieces of encoded data having different bit counts are sequentially arranged to form a bit stream.
FIG. 23 shows a flowchart representing an unpacking process using such a barrel-shift processing unit. In the conventional processor, after a bit stream having a length equal to the bit count of a register employed in the processor has been input in, an unpacking-process left-shift instruction as well as a logical right-shift instruction are executed and the barrel-shift processing unit is used to set significant bits of this word data at a logic value of 0. The word data is the input bit stream having a length equal to the bit count of a register employed in the processor. In this way, variable-length coded data having a size equal to one code is obtained. It is to be noted that in the following description, a register PAC TG is a register for storing the bit stream having a length equal to the register bit count, that is, a register for storing the word data, and a register PAC PT is a register for storing a pointer pointing to the position of a bit on the bit stream stored in the register PAC TG. The pointer stored in the register PAC PT has a value in the range 0 to N−1. Symbols REG X1 and REG X2 each denote a register used in the intermediate processing.
To put it in detail, the flowchart shown in FIG. 23 begins with a step SP1 at which a bit-streaming process is carried out to store word data to be processed in the register PAC TG. Then, at the next step SP2, the processor makes the first bit of encoded data to be extracted becomes the MSB (Most Significant Bit). To put it in detail, the processor shifts the data stored in the register PAC TG in the left direction by (N-PAC PT−1) bits and then stores the shifted data in the register REG X1. After this left-shift processing, the pointer stored in the register PAC PT is updated.
Then, at the next step SP3, the processor makes the last bit of the encoded data to be extracted becomes the LSB (Least Significant Bit). To put it in detail, the processor logically shifts the data stored in the register REG X1 in the right direction by (N-Num) bits where (N-Num) is the number of bits included in the encoded data to be extracted. Each time the data stored in the register REG X1 is shifted in the right direction by 1 bit, a logic value of 0 is inserted into the left end of the register REG X1. By shifting the data stored in the register REG X1 in the right direction in this way, the bits more significant than the first bit of the encoded data are each set at the logic value of 0. The result of the logical right shift operation is left in the register REG X1. After this logical right shift processing, the pointer stored in the register PAC PT is updated to a value indicating the number of meaningful bits included in the data stored in the register REG X1.
Then, at the next step SP4, the processor forms a judgment as to whether or not the meaningful bits of the data stored in the register REG X1 form a piece of encoded data, that is, whether or not Num is smaller than the value stored in the register PAC PT where symbol Num denotes the number of bits to be masked. If the outcome of the judgment is a negation, the processor continues the processing to a step SP5 at which the contents of the register PAC PT are updated by subtracting the number Num of bits to be masked from the contents to result in a value of (PAC PT−Num).
Upon completion of the process carried out at the step SP5, the data indicated by the register PAC PT and stored in the register REG X1 forms an entire piece of encoded data. Then, the flow of the processing then goes on to the next step SP6 to end the unpacking processing to generate a code of unpacked data.
If the encoded data following the data stored in the register REG X1 remains to be processed at the end of the unpacking processing to generate a code of unpacked data as described above as indicated by an acknowledgement outcome of the judgment formed at the step SP4, the processor transfers the remaining data to the register PAC TG and the processing described above is repeated. That is to say, if a piece of encoded data to be processed is stretched over the following bit stream for the specific data stored in the register PAC TG as indicated by an acknowledgement outcome of the judgment formed at the step SP4, the processor transfers the remaining data to the register PAC TG and the processing described above is repeated.
In this case, the flow of the processing goes on from the step SP4 to a step SP8 at which the processor shifts the data stored in the register REG X1 in the left direction by the number of supplementary bits to be added to the data stored in the register REG X1. The number of added supplementary bits is N-Num-1. Then, the data shifted in the left direction is stored back in the register REG X1. Subsequently, at the next step SP9, the following bit stream is loaded into the register PAC TG. Then, at the next step SP10, the processor logically shifts the data stored in the register PAC TG in the right direction by (N-Num) bits where (N-Num) is the number of supplementary bits to be added to the data stored in the register REG X1. Each time the data stored in the register PAC TG is shifted in the right direction by 1 bit, a logic value of 0 is inserted into the left end of the register PAG TG. By shifting the data stored in the register PAC TG in the right direction in this way, the bits more significant than the first bit of the encoded data are each set at the logic value of 0. The result of the logical right shift operation is left in the register REG X2.
Then, at the next step SP11, the data stored in the register REG X1 and the data stored in the register REG X2 are subjected to a logical sum (OR) process to concatenate the data stored in the register REG X1 with the data stored in the register REG X2 and data obtained as a result of the concatenation process is stored in the register REG X1.
Subsequently, the processor continues the processing to the step SP12 at which the contents of the register PAC PT are updated by subtracting the number Num of bits to be extracted from the contents to result in a value of (PAC PT−Num). Then, the flow of the processing then goes on to the next step SP6 to end the unpacking processing to generate a code of unpacked data.
FIG. 24 shows a flowchart representing a concrete decoding process based on the unpacking process described above. To be more specific, the processing represented by the flowchart shown in FIG. 24 is a Huffman decoding process of a bit stream. It is to be noted that processing steps identical with their counterpart steps of the flowchart shown in FIG. 23 are denoted by the same reference notations as the counterpart steps of the flowchart shown in FIG. 24 and their detailed explanation is not repeated. It is also worth noting that the maximum length of Huffman codes in the processing represented by the flowchart shown in FIG. 24 is denoted by symbol Num.
The flowchart shown in FIG. 24 begins with a step SP1 at which N-bit data to be processed is extracted from the bit stream being decoded from the bit stream and loaded into the register PAC TG. In addition, the register PAC PT is set at a value of (N−1). Then, at the next step SP2, the processor carries out the left-shift processing in the same way as described above. Subsequently, at the next step SP3, the processor carries out the logical right-shift process.
Then, at the next step SP14, the processor compares the maximum length Num of Huffman codes with the value stored in the register PAC PT in order to form a judgment whether or not the length of the meaningful data stored in the register PAC PT is smaller than the Huffman-code maximum length Num. If the outcome of the judgment is a negation, the flow of the processing goes on to a step SP15 at which, by using the data stored in the register REG X1, the processor looks up a decoding table to find a code as a result of the decoding process. Then, at the next step SP16, also by using the data stored in the register REG X1, the processor looks up a table for determination of a code length to find the length of the code found as a result of the decoding process.
Subsequently, at the next step SP17, the processor compares the code length found at the step SP16 with the value stored in the register PAC PT in order to form a judgment whether or not a portion or all of subsequent coded data is left in the register REG X1. If the outcome of the judgment indicates that a portion of all or subsequent coded data is left in the register REG X1, the flow of the processing goes on to the step SP5 at which the value stored in the register PAC PT is updated by a quantity corresponding to the resulting code. Finally, the flow of the processing goes on to a step SP6 at which the processing to process a code is finished. In order to process the subsequent code, the processor repeats the processing described above starting with the step SP1.
If the outcome of the judgment formed at the step SP17 is a negation, on the other hand, the flow of the processing goes on from the step SP17 to a step SP18 at which subsequent stream data is loaded into the register PAC TG. Than, at the next step SP19, a value of the expression (N-PAC PT+Huffman length) is recorded in the register PAC PT to update the value stored in the register PAC PT to a value according to the processing carried out at the step SP18. Finally, the flow of the processing goes on to a step SP6 at which the processing to process a code is finished.
For the specific data stored in the register PAC TG, a piece of encoded data may be stretched over the following bit stream. In this case, the result of the judgment formed at the step SP14 is an acknowledgment and the flow of the processing goes on from the step SP14 to the step SP8 at which the processor shifts the data stored in the register REG X1 in the left direction by (N-Num−1) bits. Then, the data shifted in the left direction is stored back in the register REG X1. Subsequently, at the next step SP9, the following bit stream is loaded into the register PAC TG. Then, at the next step SP10, the processor logically shifts the data stored in the register PAC TG in the right direction by (N-Num) bits. Each time the data stored in the register PAC TG is shifted in the right direction by 1 bit, a logic value of 0 is inserted into the left end of the register PAG TG. By shifting the data stored in the register PAC TG in the right direction in this way, the bits more significant than the first bit of the encoded data are each set at the logic value of 0. The result of the logical right shift operation is left in the register REG X2. Then, at the next step SP11, the data stored in the register REG X1 and the data stored in the register REG X2 are subjected to a logical sum (OR) process to concatenate the data stored in the register REG X1 with the data stored in the register REG X2 and data obtained as a result of the concatenation process is stored in the register REG X1. Subsequently, the flow of the processing goes on to the step SP15.
By the way, if a bit stream is processed as variable-length encoded data by using hardware, the look-up table is a fixed table embedded in the hardware, resulting in a lack of general-purpose characteristics. Since a bit stream is processed as variable-length encoded data by using a processor as described above, however, the look-up table can be updated to keep up with a variety of encoding techniques.
If a bit stream is processed as variable-length encoded data by using the conventional processor, however, a plurality of shift operations must be carried out. Thus, in a process of one code, a large number of cycles is required. In this connection, if the processing is carried out by adoption of a pipeline technique, a branch process will put the pipeline processing in a state of stagnation, which makes it impossible to carry out the processing by adoption of the pipeline technique at a sufficiently high speed. Thus, it is difficult to carry out the processing of a bit stream as variable-length encoded data by using a processor at a high speed and at a low power consumption. In the end, in the packing and unpacking processes described above, dedicated hardware is provided. As a result, the use of a processor in conjunction with such dedicated hardware also raises a problem of a lack of general-purpose characteristics.
In the processing represented by the flowchart shown in FIG. 23, a process to count the number of bits included in undecoded data left in the register and the branch processing carried out at the step SP4 are each a processing load. In addition, the number of steps in the processing following the branch step SP4 varies in dependence on the destination of the branch. The variations in post-branch step count are also a processing load. In addition, in the packing process carried out as an inverse process of the unpacking process, similar conditional branching processes are required so that a two-stage process is required. Moreover, in the case of the processing represented by the flowchart shown in FIG. 24, accesses to a memory are also a big overhead.
A typical method to solve the problem is proposed in Japanese Patent Laid-open No. 2001-202242. In accordance with this method, the processor is provided with an instruction for directly converting a variable-length code into a value representing the code length and the code itself. In the case of this method, however, there is raised a problem that the representation of the code itself is fixed by the instruction and the maximum bit count is restricted by the circuit scale. Thus, this method is effective only for code with a small code length such as picture data. However, the method cannot be practically applied to a process to encode sound data because a large table is required in such a process. In addition, it is actually difficult to change specifications in the future and to keep up with a plurality of systems.
In accordance with a method disclosed in Japanese Patent Laid-open No. 2001-516917, on the other hand, an address is issued for an unpacking instruction and a lookup table is referenced. In the case of this method, however, an instruction circuit requires dedicated complex circuits such as a table memory and an address generator. In addition, the method has a shortcoming that the implementation of this instruction and the number of applications for this instruction are limited.
It is to be noted that the method disclosed in Japanese Patent Laid-open No. 2001-516917 includes an extract instruction and a residue extract instruction as instructions for extracting variable-length encoded data from a bit stream. Data is extracted from a bit stream and loaded into a register by using the extract instruction and, in order to process all the data stored in the register, the residue extract instruction must be executed. That is to say, since there are different usages of these two instructions, their proper use is cumbersome.
In the case of a method disclosed in Japanese Patent Laid-open No. 2001-156645, on the other hand, a multiplexer of a shifter is used to process a variable-length bit array. However, this method has a shortcoming that, in the case of a 32-bit bus width, for example, only data having a length of up to 16 bits can be packed an unpacked.